The present invention relates generally to a semiconductor device, and more specifically to a device and a method for testing a resistance value of an on-die-termination device applied on a pad with being built in the semiconductor device.
Generally, a double data rate synchronous dynamic random access memory (DDR SDRAM) having an operating frequency above 200 MHz includes an on-die-termination (ODT) device installed on a pad so as to prevent or at least minimize any distortion in signals during transferring the signals.
In a semiconductor device using the ODT device, high speed characteristics may change in accordance to the resistance value of the ODT device.
The resistance value of the ODT device may be changed due to a fluctuations or changes in the power supply voltage, in the operation temperature, in the manufacturing process, and alike. As a result, there is a need to measure the resistance value of the ODT device so as to determine a pass/fail criteria of the measured resistance value.
The resistance value of the ODT device can be measured using a test device before the particular semiconductor device is installed in a system. However, it is particularly difficult to measure the resistance value of the ODT device using the test device after the semiconductor device is installed in a system, such as being installed in a memory module, etc.
Also, even in the case of measuring the resistance value of the ODT device using the test device, a repetitive test should be performed by using the number of pads installed with the ODT device. Accordingly, this repetitive testing protocol is unacceptably time consuming.